Most wired communication systems including a phase locked loop (PLL) with a limited pull-in range require an additional frequency acquisition loop. A phase frequency detector (PFD) which is typically used in the frequency acquisition loop requires an external reference clock such as a crystal oscillator. This causes the increase of the cost and electric power consumption of an entire system.
Various reference-less clock and data recovery (CDR) technologies directly extract data rate from input data. Also, some of the technologies make use of a frequency detector based on a finite-state machine (FSM). Another technology makes use of a frequency locked loop (FLL) based on a delay locked loop (DLL). Further another technology makes use of a line coding analyzer.
However, the technologies mentioned above have a limit in being commercialized in a high speed wired communication industry because it is difficult to manufacture a complex logic block which operates at a speed of the input data. Moreover, the logic block excessively consumes electric power and depends on the kind of an oscillator which is used and on the pattern of the input data.
Regarding a prior art voltage controlled delay line (VCDL), all of the chips cannot provide the same delay due to process voltage and temperature (PVT) variation. Therefore, this causes inaccurate frequency locking.
Consequently, demand on a technology are made, which makes it possible to easily manufacture the logic block, to reduce electric power consumption of the logic block and to provide accurate frequency locking.